/*  Camera address defintion file  */
#ifndef _USTC_CMR_DRV_H 
#define _USTC_CMR_DRV_H

#define CAMERA_BASE 				0x1800//0x02000000

#define USTC_CMIF_FIFO_SIZE		0x400

//camera interface register
#define CMR_STATUS                	(CAMERA_BASE+0x004)
#define CMR_INT_MASK              	(CAMERA_BASE+0x008)
#define CMR_INT_STATU              	(CAMERA_BASE+0x00c)
#define CMR_FIFO_SELECT 			(CAMERA_BASE+0x010)
#define CMR_DMA_REQ_MSK		 		(CAMERA_BASE+0x018)

//jpg FIFO control register
#define CMR_JPG_RESIZER_STAR			(CAMERA_BASE+0x028)
#define CMR_JPG_RESIZER_BLOCK_SIZE		(CAMERA_BASE+0x02c)

//sensor interface setting regiseter
#define CMR_SEN_IF_SEL            	(CAMERA_BASE+0x030)
#define CMR_SEN_SIGNAL_SEL        	(CAMERA_BASE+0x034)
#define CMR_SEN_CCIR656_SEL       	(CAMERA_BASE+0x038)

//view resizer setting register
#define CMR_RESIZE_CTRL             (CAMERA_BASE+0x040)
#define CMR_RESIZE_LINE             (CAMERA_BASE+0x044)
#define CMR_RESIZE_PIXEL            (CAMERA_BASE+0x048)
#define CMR_SEN_VIDEO_SEL	        (CAMERA_BASE+0x04c)
#define CMR_RESIZE_START_X_POS      (CAMERA_BASE+0x050)
#define CMR_RESIZE_START_Y_POS      (CAMERA_BASE+0x054)
#define CMR_RESIZE_END_X_POS        (CAMERA_BASE+0x058)
#define CMR_RESIZE_END_Y_POS        (CAMERA_BASE+0x05c)
#define CMR_IMAGE_MODE_SET			(CAMERA_BASE+0x060)

//resizer in/out FIFO
#define CMR_FIFO_DATA               (CAMERA_BASE+0x100)
#define CMR_FIFO_IN_DATA          	(CAMERA_BASE+0x200)

typedef struct _CMIF_T_{
	USTC_U32	reserved0;
	union _CMIF_STATUS_U_{
		USTC_U32 v;
		struct _CMIF_STATUS_T_{
			unsigned fifo_full:1;
			unsigned fifo_empty:1;
			unsigned reserved_2:1;
			unsigned busy:1;
			unsigned reserved_4:1;
			unsigned ccir656_data_tx_start:1;
			unsigned reserved_6_7:2;
			unsigned cmif_interrupt:1;
			unsigned i2c_interrupt:1;
		}bit_info;
	}status;
	union _CMIF_MASK_U_{
		USTC_U32 v;
		struct _CMIF_MASK_T_{
			unsigned fifo_ready:1;
			unsigned fifo_full:1;
			unsigned fifo_empty:1;
			unsigned ccir656_header_check_error:1;
			unsigned frame_tx_end:1;
			unsigned line_tx_end:1;
			unsigned block_tx_end:1;
			unsigned h_filter_conflict:1;
			unsigned v_filter_conflict:1;
		}bit_info;
	}mask_n;
	union _CMIF_INT_STATUS_U_{
		USTC_U32 v;
		struct _CMIF_INT_STATUS_T_{
			unsigned fifo_ready:1;
			unsigned fifo_full:1;
			unsigned fifo_empty:1;
			unsigned ccir656_header_check_error:1;
			unsigned frame_tx_end:1;
			unsigned line_tx_end:1;
			unsigned block_tx_end:1;
			unsigned h_filter_conflict:1;
			unsigned v_filter_conflict:1;
		}bit_info;
	}int_status;
	union _FIFO_CONFIG_U_{
		USTC_U32 v;
		struct _FIFO_CONFIG_T_{
			unsigned fifo_data_watermark:6;
			unsigned reserved_6_14:9;
			unsigned fifo_data_ready:1;
		}bit_info;
	}fifo_ctrl_status;
	USTC_U32 reserved1;
	union _DMA_REQ_MASK_N_U_{
		USTC_U32 v;
		struct _DMA_REQ_MASK_N_T_{
			unsigned last_request:1;
			unsigned request:1;
		}bit_info;
	}dma_req_mask_n;
	USTC_U32	reserved2[(0x28-0x1C)/4];
	USTC_U32	resizer_start;
	union _RESIZER_BLK_SIZE_U_{
		USTC_U32 v;
		struct _RESIZER_BLK_SIZE_T_{
			unsigned image_width_in_word:12;//in unit of words
			unsigned reserved_12_15:4;
			unsigned src_bus_select_AHB:1;//1 select AHB bus, 0 select Video bus
			unsigned reserved_17_19:3;
			unsigned pixel_interval_clk:3;
			unsigned reserved_23:1;
			unsigned line_interval_clk:8;
		}bit_info;
	}resizer_blk_size;
	union _SENSOR_INTERFACE_SETTING_U_{
		USTC_U32 v;
		struct _SENSOR_INTERFACE_SETTING_T_{
			unsigned select_OV_sensor:1;
			unsigned mix_VH_REF:1;
			unsigned enable:1;
		}bit_info;
	}sensor_ctrl;
	union _CMIF_SENSOR_SIGNAL_U_{
		USTC_U32 v;
		struct _CMIF_SENSOR_SIGNAL_T_{
			unsigned HREF:1;
			unsigned VEEF:1;
			unsigned YUV_format:2;//0-UYVY; 1-VYUY; 2-YUYV; 3-YVYU
			unsigned sample_rate:4;
		}bit_info;
	}sensor_signal;
	union _CCIR656_FRAME_HEADER_FORMAT_U_{
		USTC_U32 v;
		struct _CCIR656_FRAME_HEADER_FORMAT_T_{
			USTC_U8 frame_end;
			USTC_U8 line_end;
			USTC_U8 lien_start;
			USTC_U8 frame_start;
		}bit_info;
	}frame_header_format;
	USTC_U32	reserved3;
	union _RESIZER_CTRL_U_{
		USTC_U32	v;
		struct _RESIZER_CTRL_T_{
			unsigned h_filter_disable:1;
			unsigned enable:1;
			unsigned src_select_bus:1;//0 from sensor, 1 decided by bus select bit in resizer_blk_size
			unsigned v_filter_disable:1;
			unsigned scaling_rate:6;
			unsigned target_bus_select_video:1;//1 output to video bus, 0 output to AHB bus
		}bit_info;
	}resizer_config;
	USTC_U32	resizer_line;
	USTC_U32	resizer_pixel;
	union _SENSOR_FRAME_SIZE_U_{
		USTC_U32 v;
		struct _SENSOR_FRAME_SIZE_T_{
			unsigned max_pixel:12;
			unsigned reserved_12_15:4;
			unsigned max_line:11;
		}bit_info;
	}frame_size;
	USTC_U32	resizer_start_x;
	USTC_U32	resizer_start_y;
	USTC_U32	resizer_end_x;
	USTC_U32	resizer_end_y;
	union _SENSOR_IMAGE_MODE_U_{
		USTC_U32 v;
		struct _SENSOR_IMAGE_MODE_T_{
			unsigned reverse_image:1;
			unsigned data_modify_mode:3; //0-normal;1-AND;2-OR;3-ADD;4-Y(ADD)UV(replace)
			unsigned modifier_V:9;
			unsigned modifier_U:9;
			unsigned modifier_Y:9;
		}bit_info;
	}image_mode;
	USTC_U32	frame_modifier;
	USTC_U32	reserved4[8];
	union _I2C_int_status_{
		USTC_U32	v;
		struct i2c_int_status_bit_info_t_{
			unsigned read_done:1;
			unsigned write_done:1;
			unsigned ack_missed:1;
		}bit_info;
	}i2c_int_status;
}CMIF_T;

//bits for CMR INT MASK & INT STATUS
#define CMR_INT_AMSK_FIFO_READY			0x00000001
#define CMR_INT_MASK_FIFO_FULL			0x00000002
#define CMR_INT_MASK_FIFO_EMPTY			0x00000004
#define CMR_INT_MASK_CCIR_ERR			0x00000008
#define CMR_INT_MASK_FRAME_DONE			0x00000010
#define CMR_INT_MASK_LINE_DONE			0x00000020
#define CMR_INT_MASK_BLOCK_DONE			0x00000040
#define CMR_INT_MASK_HFILTER_ERR		0x00000080
#define CMR_INT_MAKS_VFILTER_ERR		0x00000100




//bits for CMR_FIFO_SELECT register
#define CMR_FIFO_SELECT_INT_WORD		0x00000000
#define CMR_FIFO_SELECT_INT_WORDS		0x00008000
#define CMR_FIFO_SIZE_FOR_VIDEO_BUS		0x00000010
#define CMR_FIFO_SIZE_FOR_DMA			0x00000008

//bits for CMR_CLK_SET register
#define CMR_CLK_SET_EXTERNAL			0x00000000
#define CMR_CLK_SET_INTERNAL			0x00000002
#define CMR_CLK_SET_RISE_EDGE			0x00000000
#define CMR_CLK_SET_FALL_EDGE			0x00000001

//bits for CMR_SEN_IF_SEL register
#define CMR_SEN_IF_SEL_CAMERA_IF_ENANLE			0x00000010
#define CMR_SEN_IF_SEL_SENSOR_IF_ENANLE			0x00000004
#define CMR_SEN_IF_SEL_SENSOR_CLK_ENANLE		0x00000010
#define CMR_SEN_IF_SEL_SENSOR_CCIR656_ENANLE	0x00000002
#define CMR_SEN_IF_SEL_SENSOR_RESET				0x00000001

//bits for CMR_SEN_SIGNAL_SEL register
#define CMR_SEN_SIGNAL_SEL_UYVY			0x00000000 
#define CMR_SEN_SIGNAL_SEL_VYUY			0x00000004 
#define CMR_SEN_SIGNAL_SEL_YUYV			0x00000008 
#define CMR_SEN_SIGNAL_SEL_YVYU			0x0000000C 
#define CMR_SEN_SIGNAL_SEL_VREF_HIGH	0x00000002
#define CMR_SEN_SIGNAL_SEL_VREF_LOW		0x00000000
#define CMR_SEN_SIGNAL_SEL_HREF_HIGH	0x00000001
#define CMR_SEN_SIGNAL_SEL_HREF_LOW		0x00000000

//bits for CMR_SEN_CCIR656_SEL register
#define CMR_SEN_CCIR656_SEL_FRAME_START  0xff000000 	
#define CMR_SEN_CCIR656_SEL_LINE_START   0x00ff0000
#define CMR_SEN_CCIR656_SEL_LINE_FINISH  0x0000ff00
#define CMR_SEN_CCIR656_SEL_FRAME_FINISH 0x000000ff

//bits for CMR_JPG_RESIZER_BLOCK_SIZE register
#define CMR_JPG_FIFO_LINE_INTERVAL      	(0xff000000)
#define CMR_JPG_FIFO_PIXEL_INTERVAL     	(0x00700000)
#define CMR_JPG_FIFO_LINE_NUMBER_8      	(0x00000000)
#define CMR_JPG_FIFO_LINE_NUMBER_16    		(0x00000000)
#define CMR_RESIZER_SRC_SELECT_SENSOR		(0x00000000)
#define CMR_RESIZER_SRC_SELECT_BUS			(0x00000004)
#define CMR_RESIZER_SRC_BUS_SELECT_AHB		(0x00010000)
#define CMR_RESIZER_SRC_BUS_SELECT_VIDEO	(0x00000000)
#define CMR_RESIZER_DST_BUS_SELECT_AHB		(0x00000000)
#define CMR_RESIZER_DST_BUS_SELECT_VIDEO	(0x00000400)

//bits for CMR_DMA_REQ_MSK register
#define CMR_IF_DMA_NORMAL			        0x00000002
#define CMR_IF_DMA_LAST              		0x00000001

//bits for CMR_RESIZE_CTRL register
#define CMR_RESIZE_CTRL_RATE			 0x000000F0
#define CMR_RESIZE_CTRL_V_SEL			 0x00000000
#define CMR_RESIZE_CTRL_V_PASS			 0x00000008
#define CMR_RESIZE_CTRL_SRC_SENSOR		 0x00000000	
#define CMR_RESIZE_CTRL_SRC_JPG			 0x00000004
#define CMR_RESIZE_CTRL_DISABLE			 0x00000000
#define CMR_RESIZE_CTRL_ENABLE			 0x00000002
#define CMR_RESIZE_CTRL_H_SEL			 0x00000000
#define CMR_RESIZE_CTRL_H_PASS			 0x00000001

extern void		ustc_cmif_scale(RESIZER_T *p_resizer,USTC_U32 winsize);
extern void 	ustc_cmif_start(USTC_U16 clk_cfg, USTC_U32 wFrameSync);
extern void		ustc_cmif_close(void);
extern void		ustc_cmif_effect(USTC_U32);
extern USTC_U32	ustc_cmif_int_status(void);
extern void 	ustc_cmif_int_clear(USTC_U32 status);

#endif  /*CMR_DEV_H*/
